• AMBA AHB SLAVE MULTIPLE SPLIT RESPONSES TO SINGLE MASTER

    Can the AMBA AHB Slave give multiple SPLIT response again to the AHB Master that has been given SPLIT response before and after updating hsplit signal for that Master by the Slave?

  • AMBA AHB5 : Stable Between Clock Question

    Hi All,

    I have a question on AMBA5 AHB feature : Stable_between_Clock property

    The AMBA5 AHB Specification describes:

    Signals that are described as being stable are required to remain at the same value when sampled at different rising clock edges in an…

  • AMBA AHB

    Hi ,

    In AHB specs, There is one note as below.

    Note

    Every slave must have a predetermined maximum number of wait states that it will insert before it backs off the bus, in order to allow the calculation of the latency of accessing the bus. It is recommended…

  • In AMBA AHB, If EBT(early burst termination) is happened in address phase of a transfer then it's data phase will be driven or not?

    Hi,

       I have a question on AMBA AHB, Let us assume we are firing INCR4 burst from master M1.

      Let us assume  EBT is happened during 2nd transfer address phase of INCR4 burst (i.e Master M1 lost its grant without driving of its data phase and…

  • AMBA

    Hello....!!!

    Can anyone tell the minimum and maximum frequency or bandwidth on which AMBA AHB, APB, AXI and CHI and ACE can work successfully?

  • What does an AHB slave do after issuing an ERROR, if the master decides to carry out the remaining transfers of the burst?

    The spec simply states that a master may cancel a burst after receiving an ERROR response for one of its transfers or continue with the remaining transfers.

    The spec does not go on to state what the slave is supposed to do in that case though. Should it…

  • AMBA AHB TRANSFER CONTINUE AFTER ERROR RESPONSE

    Hello everyone,


    Please describe me the transfer continuation process after ERROR response from the slave.ERROR response.jpg

    As shown in the above figure at cycle T4 if MASTER identifies the ERROR response from the SLAVE. Now, if the MASTER wants to continue the current transfer…

  • TRANSFER CONTINUE AFTER ERROR RESPONSE FROM SLAVE

    Hello everyone,

    I want to understand the transfer continuation process from AHB MASTER during ERROR response from AHB SLAVE.

    As specified in the AMBA Specifications (Rev 2.0) IHI0011A_AMBA_SPEC.pdf section 3.9.4 page no 3-23 :

    3.9.4 Error response

    If a slave…

  • Significance of [MS] and [LS] in big-endian data bus in AHB5 Specification

    Hi,

    As indicated in few previous answers (Link Given below) on the big-endian, I believe that the big-endian type in AHB-Lite Spec is BE32. And further the AHB5 Spec added another type of big-endian as BE8. Hence, the active byte lanes for a 32-bit big…

  • Question on duration of hsel in AHB

    Hi,

    My question is about duration of hsel in AHB. While performing a write operation to a particular slave, if hsel for the slave is asserted (hsel=1) in the address
    face and is deasserted (hsel=0) in the data phase, will it guarantee that data is written…