• Cache type and cache operation sequence

    I have a shared memory in DDR  --- shared between two separate ARM execution environments (say A and B)  in a heterogeneous compute SoC.

    SW on each execution units (A and B) Reads and Writes to this shared location (imagine a array/matrix that…

  • SC and SD states in case of ReadNoSnoop transactions

    Hi All,

    This question is regarding "ReadNoSnoop" transaction of AMBA- ACE protocol.

    If "ReadNoSnoop" transaction is used in a region of memory that is not shareable with other masters, then how can the cache line have have "Shared Clean" or "Shared…

  • Bare Metal Input/Output - Documentation?

    Does anyone know of an Idiot's Guide to this topic? In particular, how does a processor with no special I/O instructions issue a request, e.g. to a serial output device to output "Hello, World"? And how does Memory-Mapped I/O work in detail? Where is…

  • AXI4: Wider transactions than BUS width allowed?

    Hi AXI-experts,

    Does AX4 support burst sizes larger than the bus width?

    Narrow transactions are allowed, but do wider transactions also work?

    Best regards,

    Robert

  • ACE - ReadNoSnoop transaction

    In ACE Specifications - ARM IHI 0022E, in ReadNoSnoop transactions how is the following other state of cacheline

    given on page number C4-197 transaction permitted :

    Start State  - ShareClean

    RRESP[3] - 0, RRESP[2] - 0

    End State - Invalid or UniqueCl…

  • MakeUnique Transaction (ACE protocol)

    Hi.,

    As we know that there is a MakeUnique transaction in ace protocol, can anyone tell me how we can initiate this transaction..? I mean what is the respective signal in AXI4/ACE that allows us to set a master to initiate this MakeUnique transaction.…