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Users of Arm processors can be all over the planet, and now they have a place to come together. The processors community is the place to be all things processor-related.
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Unanswered questions
translation table APTable permission problem
Not Answered
9 hours ago
Regarding Visibility of Multi Master ACE-Lite System
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9 hours ago
the linux kernel will be hung here as long as there are more than one core inside one cluster
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2 months ago
A72 Invalidate dirty cache line (DC IVAC)
Not Answered
17 days ago
TrustZone- Confidential Computing- TEE
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1 month ago
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data cached during level-2 page walk
0
2719
views
2
replies
Latest
1 month ago
by
XNoOp
Answered
Can I change the frequency of the generic timer in armv8?
0
2487
views
2
replies
Latest
1 month ago
by
Zili
Not Answered
Jitter in a square wave generated by using GPIO.
0
2421
views
1
reply
Latest
1 month ago
by
42Bastian Schick
Suggested Answer
io coherency and shareability
0
Cache coherency
Cache Coherent Interconnect
coherency
3497
views
1
reply
Latest
1 month ago
by
Christopher Tory
Answered
How to do the ARM state change between 64-bit and 32-bit?
0
32-bit
AArch64
Armv8-A
64-bit
AArch32
47470
views
10
replies
Latest
1 month ago
by
Su40mmer
Not Answered
Cortex-A35 performance for DDR3 read accesses
0
Cortex-A35
performance
5106
views
8
replies
Latest
1 month ago
by
Gael
Not Answered
compiler optimization options for ARMv8 GCC compiler on ARM cortex a53 (bare metal application)
0
Cortex-A53
AArch64
Optimization Solution
Armv8-A
GCC
NEON
8046
views
9
replies
Latest
1 month ago
by
XNoOp
Not Answered
how to upgrade juno from android9 to android10
0
Juno Arm Development Platform
Android
3111
views
0
replies
Started
1 month ago
by
aaron.gao
Not Answered
A53 Erratum 820719 missing from official ARM errata document list
0
Cortex-A53
3244
views
0
replies
Started
1 month ago
by
ekta
Not Answered
the width of AXI ID conflict
0
3554
views
1
reply
Latest
1 month ago
by
Colin Campbell
Suggested Answer
Enable and disable MMU page table caching in L2
0
3707
views
3
replies
Latest
1 month ago
by
XNoOp
Not Answered
Debugger cannot execute cast and vectorization commands
0
Armv8-A
Debugger
3752
views
3
replies
Latest
1 month ago
by
42Bastian Schick
Not Answered
How to use L2 cache as memory from ACP access on zynq Cortex A9 ?
0
6219
views
10
replies
Latest
1 month ago
by
XNoOp
Not Answered
Pragma ignoring error when using arm-linux-androideabi-4.9 toolchain
0
3177
views
1
reply
Latest
1 month ago
by
42Bastian Schick
Not Answered
How to check whether the executing program uses cache memory for low latency?
0
4790
views
1
reply
Latest
1 month ago
by
XNoOp
Not Answered
How does the memory regions are mapped in A72 cortex?
0
5315
views
2
replies
Latest
1 month ago
by
XNoOp
Not Answered
L2 cache error injection and Prefetch Abort
0
3409
views
1
reply
Latest
1 month ago
by
XNoOp
Not Answered
Penalty estimate of TLB miss or table walk in armv8
0
3286
views
2
replies
Latest
1 month ago
by
XNoOp
Not Answered
Seeking more information on SError on A53 core
0
3841
views
2
replies
Latest
1 month ago
by
KPK
Not Answered
Why L1 cache associativity DOUBLED and index method CHANGED from the programmer's point of view?
0
Cache
3789
views
4
replies
Latest
1 month ago
by
42Bastian Schick
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