Hi, accorting to the reference manual of cortex A7 https://static.docs.arm.com/ddi0464/f/DDI0464.pdf
pagina 243, what event number i neet to select to count all the DRAM access (read / write)?
The core does not know anything about DRAM. The best guess is to count L2 cache fills and L2 cache write back (which likely reads/writes from/to DRAM).
The events data memory access what means? the event external memory request what means? There is some document that details all the events? becasuse I found only table that nor is explicative.
Check out DDI0406C, it explains all events.
I agree to your point. Can you explain me then what is the significance of Bus Access Write and Bus access Read in A55 and A76? Why there are two seperate events if they are counting the same?
Why should these two be the same? One is read the other write.
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