In AXI, does the rising and falling edge of the WVALID signal signify the start and end of a write burst? Can the WVALID signal go low before the write request for all the transfers in that burst are issued?
You'll find xREADY/xVALID signals on each channel, and they are used for hand shaking.
The receiver asserts xREADY when it is ready to receive a transfer. The sender asserts xVALID when there is valid "stuff" (*) on the channel. A transfer takes place when both are asserted at the same time.
A burst is made up of a number of transfers. These could be back-to-back, by which I mean both WVALID and WREADY being asserted continuously for a number of a number of cycles. Or, there could be gaps between each transfer, where either (or both) WVALID/WREADY are de-asserted.
(* I say "stuff" because what is being sent/received depends on the channel. For the W channel it's written data.)
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