In AXI, does the rising and falling edge of the WVALID signal signify the start and end of a write burst? Can the WVALID signal go low before the write request for all the transfers in that burst are issued?
No, WVALID does not have to be asserted continuously for a write burst. It's obviously better for bandwidth utilisation if a write transaction sees all of it's data transfers happen back to back, but the specification does not mandate it. For example, in a 4 beat burst, the master could transfer 2 beats, take WVALID low for a few cycles and then take it high again to complete the last 2 beats.
Hope that answers your question.
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