Hello
I'm eager to know about Cortex M0 instruction sets .
I've write a piece of code :
GPIOA->BSRR=GPIO_PIN_5;
GPIOA->BRR=GPIO_PIN_5;
and assembly code is :
// GPIOA->BSRR=GPIO_PIN_5;
0x8000214: 0x6001 STR R1, [R0]
// GPIOA->BRR=GPIO_PIN_5;
0x8000216: 0x6101 STR R1, [R0, #0x10]
As in this document says "STR " takes 2 cycles.
But when i simulate in IAR and check cyclecounter it's increment by one .
it means it takes one cycle .
now i'm wondering my simulation has problem or i misunderstood the document .
Best Regards
Morteza
Hi,
Although SysTick is suspended when halting, the cycle timing of single stepping is more complex.
After the processor is resume from halting, it has to fetch instruction, decode and then execute, and then the processor stops again and SysTick is stop.
As a result, the total number of clock cycles is longer with such measurement method is not showing the execution timing of normal code execution, where the instruction fetch and decode can pipelined with other instruction's executions.
regards,
Joseph
Hi jyiu
do you have any idea about my last post .
Thanks Joseph
while(1){
};
0x8000970: 0xe7fc B.N 0x800096c
i debug it in Disassembly view and monitor systick register
before i press "Step into" on the first line the systick register hase 31983 value
after execute first line it changed to 31977 means 6 cycles !
for second line it change to 5 cycles !
and third line the systick doesn't change !
For real hardware, normally you need to add some SysTick control code to do it. But it is quite simple to do. Debug tools can access to the SysTick registers, but will not know when you want to start and stop timing measurement. So putting the measurement control code inside the source code is easier.
For instruction set simulators in development tools, it depends on the implementation of the simulator.
joseph
Hi joseph
Thank you .
"For instruction set simulation in development tools, it does not always give accurate timing. So it can varies from real hardware."
Can i use systick with debugging tools (not simulation tools) for measuring cycles ?
Hi all,
Instruction cycle timing on Cortex-M3/M4 are different from Cortex-M0.
In Cortex-M0, LDR and STR takes two cycles.
In Cortex-M0+, then it depends on whether the access is targeting an address location on the single cycle I/O interface.
In Cortex-M3/M4:
- LDR takes two cycles, except when pipelined with another memory access instruction. In that case, the first access takes 2 cycles, the second one takes 1 cycle.
- STR takes single cycle (for bufferable memory regions) or two (for non-bufferable region).
Please note all these cycle counts assume zero wait state in the memory system.
For instruction set simulation in development tools, it does not always give accurate timing. So it can varies from real hardware.
Thank you
But as i read there jyiu said :
"For best performance, in general pipeline LDR and STR are good for Cortex-M3/M4. (Not applicable to Cortex-M0, M0+ , M7)"
Hello mori64,
please refer to Re: Instruction timings - arm cortex m3.
Best regards,
Yasuhiko Koumoto.
Hello Yasuhiko
Thanks for your reply
As i see here there are all 2 cycles
you mentioned to the "consecutive" .
could you please describe a bit more about this .
Hi mori64,
consecutive STRs take one clock cycle.
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