From the TRM of the Cortex A9 we can read in section 7.4.3 Cortex-A9 behavior for Normal Memory Cacheable memory regions:
SCTLR.C=1 The Cortex-A9 Data Cache is enabled. Some Cacheable accesses are still treatedas Non-Cacheable:• all pages marked as Write-Through are treated as Non-Cacheable• if ACTLR.SMP=0, all pages marked as Shared are treated as Non-Cacheable.
SCTLR.C=1 The Cortex-A9 Data Cache is enabled. Some Cacheable accesses are still treated
as Non-Cacheable:
• all pages marked as Write-Through are treated as Non-Cacheable
• if ACTLR.SMP=0, all pages marked as Shared are treated as Non-Cacheable.
I am only running on a single core, and I want to enable L1 and L2 caches without enabling the SCU (I have issues with that at the moment).
I tried to set ACTLR.SMP to 1 with the SCU disabled without any success so far (I get memory corruption), so how should I set my MMU to get L1 and L2 caches on ?
I think I need to map my pages with the S bit set to 0, is that correct ?
Hi vsiles,
Yep, marking memory as Non-Shareable implicitly means that you are the only core/device in the system that needs to see that data. As you progressively increase the Shareability, you're telling the system that it needs to ensure that data is pushed further and further out. ACTLR.SMP=0 implies there is no system cache coherency, so the only way to stay consistent with other devices Sharing data is to treat it as Non-Cacheable.
However I'd rather fix your problems getting the SCU working. Did you invalidate your SCU tags before enabling it? Even for a single core, you should really have the SCU enabled and ACTLR.SMP=1 and ACTLR.FW=1 (which the TRM helpfully forgets to tell you).
The SCU will deal with forwarding coherency requests to other cores or not depending on their presence/power control, and you won't receive or execute any if no other cores are up, but not setting those bits does have a significant effect on the MMU, TLBs and caches on most ARM Cortex-A cores and essentially makes the ACP useless on the Cortex-A9. You should be following the steps in:
ARM Cortex‑A9 MPCore Technical Reference Manual : 5.3.4 About multiprocessor bring-up
.. and set ACTLR.FW at the same time you set ACTLR.SMP.
Ta,
Matt
mwsealey I noticed that I don't have any issue running code in svc mode, but I have a lot of errors that seems L1 cache related into my user mode code.
To test this, instead of switching back to a user application at the exit of my kernel, I jumped back to the usual "svc" entry point, read/fill a 2 Mb array with random stuff and loop forever.
This code runs perfectly.
Do you have any idea or suggestions to think I might focus on that would explain why I get cache errors in kernel mode but not in user mode ?
My kernel is mapped as Section, Normal Memory WB WA, Shared, Global
My apps are mapped as 4k Page Tables, Normal Memory, WB WA Shared, Non Global
Best regards,
Vincent
I replaced my TLBIALLIS by ASID with plain TLBIALLIS and it works... I'll try to understand what's happening with my ASID management.
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