Hi,
I start to learn and program TZC-400 in FVP Cortext57-A Base platform with DS-5, and encounter something that I don't understand.
I start the FVP as non-secure mode by using the paramter "bp.secure_memory = false". Then I poll TZC's gate_keeper register and get 0 for all bits. According to the document, this means all the gates are shutdown for slave, so no access can go through TZC. But then if I use CPU to write a data pattern to a DRAM, it manages to do that. I can see the pattern in the memory.
How could this hapeen ? Did I misunderstand any thing ?
Thanks in advance !
Xinwei
The secure_memory = false parameter is a model specific "cheat" that doesn't model hardware. Setting this parameter bypasses the TZC functionality and allows secure and non-secure access to the memory.
If you want to program the TZC they you need to set secure_memory = true and then the TZC will follow the reset behaviour as in the TZC-400 TRM. This means that you cannot access RAM behind the TZC until SW configures and opens the gates.
hope that helps.
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