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Getting started on Cortex A5 interrupts

I'm new to Cortex A5 and I'm trying to figure out how the interrupts work.

From my understanding, the Cortex A5 starts in secure mode and I don't change it. Now I set up the "secure interrupt controller" (of course only accessible in secure mode) and let it fire an FIQ interrupt. Now, from within the interrupt, should I be able to talk to the "secure interrupt controller", or does that require changing the SCR first, so the FIQ gets me to "monitor mode" instead? Is there any way to access secure peripherals from within FIQs?

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  • Cortex-A5 MPCore has an integrated GICv1 interrupt controller.  In GICv1 (and also GICv2) all the registers are memory mapped.

    Taking about the "secure interrupt controller" is possibly a little misleading.  The GIC is TrustZone aware.  Both Secure and Non-secure software will interact with the same GIC, but the GIC will limit Non-secure software to only be able to configure/handle Non-secure interrupts.  Software running in Secure state can access both kinds of interrupts (although you wouldn't typically handle Non-secure interrupts in Secure state).

    To get your specific question about the SCR...  The SCR.I/F bits control whether an interrupt should be taken to IRQ mode in the current Security state or cause entry to Monitor mode.  Typically you'd only want to enter Monitor mode if you needed to change Security state before dealing with the interrupt.  For instance, you are in Non-secure and you receive a Secure interrupt.

    In your case that shouldn't be necessary.  You've only configured Secure interrupts and you're already in Secure state.

    In terms of accessing the peripheral, I assume it's memory mapped.  So yes, assuming your translation tables are set up correctly.

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  • Cortex-A5 MPCore has an integrated GICv1 interrupt controller.  In GICv1 (and also GICv2) all the registers are memory mapped.

    Taking about the "secure interrupt controller" is possibly a little misleading.  The GIC is TrustZone aware.  Both Secure and Non-secure software will interact with the same GIC, but the GIC will limit Non-secure software to only be able to configure/handle Non-secure interrupts.  Software running in Secure state can access both kinds of interrupts (although you wouldn't typically handle Non-secure interrupts in Secure state).

    To get your specific question about the SCR...  The SCR.I/F bits control whether an interrupt should be taken to IRQ mode in the current Security state or cause entry to Monitor mode.  Typically you'd only want to enter Monitor mode if you needed to change Security state before dealing with the interrupt.  For instance, you are in Non-secure and you receive a Secure interrupt.

    In your case that shouldn't be necessary.  You've only configured Secure interrupts and you're already in Secure state.

    In terms of accessing the peripheral, I assume it's memory mapped.  So yes, assuming your translation tables are set up correctly.

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