how can i design APB to AHB bridge ??

i want to design a bridge between APB  and AHB in verilog

my design consists of :

1. control clock unit (ccu)   // using APB

2. my DUT contains registers module & functional module  // using AHB

3. tow memories (source memory and detestation memory)

so i need to use a APB to AHB Bridge

tb-dtc.v
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