Hello,
I am working on Cortex-A53 and using Cortex-A53 DSM Model in my design. We are getting Data Abort exception on a read to ROM address and ESR_EL3 register showing its a DECERR External error. MMU and Cache both are not enabled at this point where Abort exception is coming as its just start of the boot. On AXI3 I could see all the previous transaction are successfully completed but this load transaction is not visible on AXI. Can anyone suggest what can be possible reason for this.
Cheers,
Can you post your ESR_EL3/FAR_EL3? Is it Synchronous or Asynchronous External Abort? If you don't see the request go out to AXI, it's likely Asynchronous External abort.
When MMU is off, you cannot make unaligned accesses with LDR/STR. You can check the assembly if the STR is on an unaligned address. If so, you can use LDRB/STRB instead
I wonder if bits [3:0] of EsR_EL3 will give some more info on the fault type. Have you checked that?
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