Dear sirs,
I read ACE specification and ARM processor documents for ACP explanation. I always have some questions about ACP.
As soon as you know, ACP exists in SCU for data coherency.
Q1: The document says that ACP usually connects to a DMA or cryptographic engine, so why does it connect to them?
Q2: who starts ACP port to transfer data from where to where?
Q3: How does ACP implement coherency in multi-core processor?
Thanks.
Cray
No.
The external master (e.g. DMA) does not itself have cache coherency, it gains it by being connected via the ACP.
What I meant by it being uncached, is the ACP only has visibility of the master's bus transactions. Imagine the external master had a cache. It reads an address, which causes a line fill. The line fill bus transaction goes via ACP, meaning it gets a cache coherent copy back. After this processor writes the address, changing the value. But the external master has no knowledge of this - and keeps using the copy in its caches. Hence ACP works well with uncached masters.
Hi Martin,
Thanks for your explanation. Got it.
cray