Hello,
i was wondering if the voltage levels for dvfs states are fixed at the design time. For example for Cortex A7 or A15. Is this information available?
Thank you.
DVFS is not part of the logical design at all. The voltage ranges available depend (at the high level) on the silicon process and the voltage regulator used, but in reality may also (at the low level) depend on the specific chip (as not all parts of a silicon wafer are equally fast). Any information related to DVFS therefore needs to be sourced from the chip manufacturer.
HTH, Pete
Do you think that Samsung is willing to give that information?
It's information that most device manufacturers will need, so I would assume it is part of their data sheets, but not sure if they are available publicly. You''ll have to ask Samsung for a definitive answer.
Cheers, Pete
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