Basically I want to provide delay of 15 clock cycles for writing and reading through axi4 bus .Is it possible?
Hi,
I think that you can make 15 cycle signal mask for both WVALID and WREADY.Please see below.
Best regards,Yasuhiko Koumoto.
Thank you so much for your replies.
I am using memory controller block(Xilinx) and I need to delay the read and writes for 15 clock cycles so that I can modify the data being written to memory. Xilinx uses AXI bus . So I was thinking to delay the data when present in AXI bus. I have tried to delay the reading and writing but it has corrupted the data. I need to know where can I delay the data in AXI bus. And I have not made register slice myself . I was using the inbuilt AXI register slice to do so.
Also as said by you if i try to delay the data between aw and w channel. Then how will my system behave under burst mode. Because according to me in burst mode aw channel will be utilised once. As consecutive addresses will be calculated by the axi itself.and therefore i wont be able provide delay to each data in burst mode.
All suggestions are welcome
Regards
Preet
Also as said by @jd_ if i try to delay the data between aw and w channel. Then how will my system behave under burst mode. Because according to me in burst mode aw channel will be utilised once. As consecutive addresses will be calculated by the axi itself.and therefore i wont be able provide delay to each data in burst mode.
Also as said by @jd_ if i try to delay the data between aw and w channel. Then how will my system behave under burst mode. Because according to me in burst mode aw channel will be utilised once. As consecutive addresses will be calculated by the axi itself
Hi preet729,
As "yasuhikokoumoto" says, we would need to know what is driving this requirement before anyone could suggest how to achieve this.
The interconnect logic between your master and your slave should be trying to pass information as quickly as possible, so it would be rare to see anything intentionally adding 15 cycles of delay.
Instead my first thought would be that if a master or a slave needs to delay any transfer completing on any channel, both the transfer source and the transfer destination have full control over the transfer timings using the AXI VALID and READY handshake signals.
So if for example your slave required at least 15 cycles between an AW channel transfer and the first W channel transfer, the slave can simply hold WREADY low for that amount of cycles.
Register Slices are there to break timing long paths, so adding up to a couple of clock cycles of latency depending on the design, but not 15.
You can add buffers in some ARM interconnects to data channels, but these will still try to pass the data from source to destination as soon as possible, so just adding one cycle of registering before making the data available to the destination device. Write data channel buffers can have something called "tidemark" levels which will stall the buffered write data until sufficient write data is buffered, or until the WLAST data transfer, but again not really guaranteeing any 15 cycle requirement.
So I would suggest that the component needing the 15 cycle delay should use the available READY and VALID handshake signals to implement the delay, unless you can explain why that isn't possible in your system, and what is driving this requirement.
JD
I cannot catch your intention.Please let us know it.Because latencies from "a read address valid" to "the corresponding read data responses" or from "a write address valid" to "the corresponding write response" would be unpredictable, is there any reason to add 15 cycle delay?Do you want AT LEAST 15 cycle delay?Do you design such a register slice by yourself?
Or do you want to by such a register slice?I think if you want to do so, you can only do it.What is the back ground of your question?
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