Basically I want to provide delay of 15 clock cycles for writing and reading through axi4 bus .Is it possible?
Hello Preet Kaur Walia,
can you tell me the status of your work?Was your problem solved?If you have already solved it, please let me know your methods.
Best regards,
Yasuhiko Koumoto.
it's sad news.By the way, you said that if the following logic was used, it went well.
always@(posedge CLK) begin if(~ARESETN) FIRST_WDATA_MASK <= 0; else if(AWVALID & masked_AWREADY) FIRST_WDATA_MASK <= 1; else if(WADDR_DONE & WREADY) //change FIRST_WDATA_MASK <= 0; end
If it is correct, I guess that your master would not assert WVALID until getting WREADY from the slave. But it would violate the AXI specs.Can you confirm it?If you can confirm it, I should compromise the description above.To the contrary, if your slave would not assert WREADY until getting WVALID from the master, "else if(WADDR_DONE & WREADY)" would be replaced for "else if(WADDR_DONE & WVALID)".
By the way, I have found something was wrong."else if(AWVALID&masked_AWREADY)" would be strange (also in the read case).I'm sorry but I think masked_AWREADY should be AWREADY.
I am afraind WADDR_DONE would not become "1" with the previous description.Therefore, the logics would be the following.
always@(posedge CLK) begin if(~ARESETN) WADDR_DONE <= 0; else if(AWVALID&AWREADY) WADDR_DONE <= 1; else if(BVALID&BREADY) WADDR_DONE <= 0; end always@(posedge CLK) begin if(~ARESETN) FIRST_WDATA_MASK <= 1; else if(AWVALID&AWREADY) FIRST_WDATA_MASK <= 1; else if(WADDR_DONE&(wcounter==4'hf)) FIRST_WDATA_MASK <= 0; end always@(posedge CLK) begin if(~ARESETN) wcounter <= 4'h0; else if(WADDR_DONE&masked_WVALID&masked_WREADY) wcounter <= 4'hf; else if(wcounter!=4'h0) wcoubter <= wcounter -1 ; end assign mask_pre = (wcouner != 4'h0); assign WREADY_mask = FIRST_WDATA_MASK | mask_pre; // CHANGE! assign WVALID_mask = mask_pre; // CHANGE! assign masked_WVALID = WVALID & ~WVALID_mask; // RVALID for master assign masked_WREADY = WREADY & ~WREADY_mask; // RREADY for slave assign masked_AWREADY = ~WADDR_DONE & AWREADY; // this make outstanding 1
How about them?I'm sorry for you inconvenience.
Sir
None of the solutions seem to work and I am not able to figure out the reason.
Regards
Preet Kaur Walia
Hello Preet Kaur Walia.
I doubt your suspicion (or maybe experiment result?) "if(WADDR_DONE&WVALID&WREADY)" might not become true because WVALID and WREADY should independent according to "A3.3.1 Dependencies between channel handshake signals" of AXI specs.
Actually, there would be some wrong scenarios with your implementation of "else if(WADDR_DONE & WREADY)" and the reset value was '0'.
If First_WDATA_Mask reset value was '0', it cannot handle the following scenario.
I think almost all case would be the <2> timing.
And "else if(WADDR_DONE & WREADY)" would not handle the following scenario.
This would be the same situation with "else if(WADDR_DONE & WVALID)".
So, I would like to propose the following description.
always@(posedge CLK) begin if(~ARESETN) FIRST_WDATA_MASK <= 1; // new change else if(AWVALID & masked_AWREADY) FIRST_WDATA_MASK <= 1; else if(WADDR_DONE & WREADY & WVALID) // should not change FIRST_WDATA_MASK <= 0; end
How about this?
Otherwize.
always@(posedge CLK) begin if(~ARESETN) FIRST_WDATA_MASK <= 1; // new change else if(AWVALID & masked_AWREADY) FIRST_WDATA_MASK <= 1; else if(WADDR_DONE & (wcount==4'hf)) // new change FIRST_WDATA_MASK <= 0; end
I have done the following change to the code and it seems to work.
As we donot know that awready will be high before or after wvalid. Therefore there is possibility that first data mask will remain 1 as this condirion may not get true
the changed code
regards
I am sorry. I forget the current First_WDATA_Mask would be too late to stop the first data cycle.
I think that if the reset value of First_WDATA_Mask was '1' and it would become '1' at every writing done (BVALID&BREADY), it might go well.
always@(posedge CLK) begin if(~ARESETN) FIRST_WDATA_MASK <= 1; else if(BREADY&BVALID) FIRST_WDATA_MASK <= 1; else if(WADDR_DONE&WVALID&WREADY) FIRST_WDATA_MASK <= 0; end
The write is still not working.
i have a doubt. According to the timing you have assumed it states that during a write transaction the wvalid will be asserted after awready.
But in the manual ambaaxi it has been quoted that "
It is important that during a write transaction, a master must not wait for AWREADY
to be asserted before driving WVALID. This could cause a deadlock condition if the
slave is conversely waiting for WVALID before asserting AWREADY.
"
Then the logic would fade.
in the write case, you should swap the meaning of data READY and VALID.That is, RREADY to WVALID and RVALID to WREADY conversions will be needed.
always@(posedge CLK) begin if(~ARESETN) WADDR_DONE <= 0; else if(AWVALID&masked_AWREADY) WADDR_DONE <= 1; else if(BVALID&BREADY) WADDR_DONE <= 0; end always@(posedge CLK) begin if(~ARESETN) FIRST_WDATA_MASK <= 0; else if(AWVALID&masked_AWREADY) FIRST_WDATA_MASK <= 1; else if(WADDR_DONE&WVALID&WREADY) FIRST_WDATA_MASK <= 0; end always@(posedge CLK) begin if(~ARESETN) wcounter <= 4'h0; else if(WADDR_DONE&masked_WVALID&masked_WREADY) wcounter <= 4'hf; else if(wcounter!=4'h0) wcoubter <= wcounter -1 ; end assign mask_pre = (wcouner != 4'h0); assign WREADY_mask = FIRST_WDATA_MASK | mask_pre; // CHANGE! assign WVALID_mask = mask_pre; // CHANGE! assign masked_WVALID = WVALID & ~WVALID_mask; // RVALID for master assign masked_WREADY = WREADY & ~WREADY_mask; // RREADY for slave assign masked_AWREADY = ~WADDR_DONE & AWREADY; // this make outstanding 1
The read is working fine but write is not.
As you mentioned the write will work similarly but it does not.
If I do a single write it is getting written on memory without delay(I am assuming the first data mask is not working for it)
Burst is not working.
I am working on the read and write as per your suggestions.
I shall mask arready such that handshaking is not possible.
Yes, you shall.
Also by making outstanding one you mean that the master cannot send second address before first data from first read transaction is read back?
Also by making outstanding one you mean that the master cannot send second address before first data from first
read transaction is read back?
Yes, it does.
Best regards,Yasuhiko Koumoto.
As you can see from the diagram I have taken from the manual of AMBAaxi it states that overlapping read bursts can occur(second address can be sent) without the first data being read back. I have thought of an alternative to this option:
shall i stop the handshaking
axhandshake=arvalid & arready;
instaed
axhandshake=arvalid & mask_arready;
Firstly,the write circuit you sent to me..will be applicable for delaying each dataword in a write transaction(same situation as read).
No, it were not. The write logics insert 15 cycle delay one time.However, my new logics which were shown by HDL in the read case will be applicable to the write channel. I think by replacing 'R' for 'W', it will be OK.
This masked_arready will be used by used to mask arready or just in the always block you have described in your code? I am not able to understand this statement.
The aim of the code is to limit the number of read outstandings to one.If the master would issue more than one read addresses before responding the first data, the basic assumption of my logics would be destroyed.
hankyou sir .
I have a few doubts
Also I am not able to understand the cpncepr of arready.
from what I have understood
assign masked_ARREADY = ~ADDR_DONE & ARREADY; // this make outstanding 1
This masked_arready will be used by used to mask arready or just in the always block you have described in your code?
I am not able to understand this statement. further I have understood the working.
thank you for the confirmation.My previous idea is wrong because a master will accept the first data response without delay.I think the desired timing would be as following.
To realize the timing I would like to the Verilog descriptions like below.
always@(posedge CLK) begin if(~ARESETN) ADDR_DONE <= 0; else if(ARVALID&masked_ARREADY) ADDR_DONE <= 1; else if(RLAST&RVALID&RREADY) ADDR_DONE <= 0; end akways@(posedge CLK) begin if(~ARESETN) FIRST_DATA_MASK <= 0; else if(ARVALID&masked_ARREADY) FIRST_DATA_MASK <= 1; else if(ADDR_DONE&RVALID&RREADY) FIRST_DATA_MASK <= 0; end akways@(posedge CLK) begin if(~ARESETN) counter <= 4'h0; else if(ADDR_DONE&masked_RVALID&masked_RREADY) counter <= 4'hf; else if(counter!=4'h0) coubter <= counter -1 ; end assign mask_pre = (couner != 4'h0); assign RVALID_mask = FIRST_DATA_MASK | mask_pre; assign RREADY_mask = mask_pre; assign masked_RVALID = RVALID & ~RVALID_mask; // RVALID for master assign masked_RREADY = READY & ~RREADY_mask; // RREADY for slave assign masked_ARREADY = ~ADDR_DONE & ARREADY; // this make outstanding 1
HTH,Yasuhiko Koumoto.
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