Basically I want to provide delay of 15 clock cycles for writing and reading through axi4 bus .Is it possible?
Sir
My write delay is working fine if I delay wready in my write channel. I have a doubt. If I am doing continous write and then I read continously, it is working fine(my each data word is getting delayed) but not in the case when I perform single read and single write. Is it that if I am not performing bursts(I do a single write and I read single data) the flow of data between different modules in AXI different to that to a single read and single write.
Regard
Preet Kaur Walia
Hello,
I think your code might support only the 4 burst case from the description below.
always @(posedge clk) begin if (w_complete_ns | reset) begin cnt <= {C_CNT_WIDTH{1'b1}}; end else if (whandshake_i) begin cnt <= cnt - 1'b1; end end always @(posedge clk) begin if (reset | w_complete_ns) begin subburst_last <= 1'b0; end else if ((cnt == {{C_CNT_WIDTH-1{1'b0}},1'b1}) & whandshake_i) begin subburst_last <= 1'b1; end end
Best regards,Yasuhiko Koumoto.