Basically I want to provide delay of 15 clock cycles for writing and reading through axi4 bus .Is it possible?
Hi
I have made a bridge between the register slice and write channel and added the delay code in that. That is I am delaying the wready signal in that. My doubt was that will delaying workif we only delay the wready signal. Others would not be required.
Regards
Preet
Hello,
don't you want to delay only the wdata for a slave, do you?
Do you want to add delay for the other signals?
Could you tell me the reason why the delaying won't work if we only delay the wready signal?
Best regards,
Yasuhiko Koumoto.
Sir
My write delay is working fine if I delay wready in my write channel. I have a doubt. If I am doing continous write and then I read continously, it is working fine(my each data word is getting delayed) but not in the case when I perform single read and single write. Is it that if I am not performing bursts(I do a single write and I read single data) the flow of data between different modules in AXI different to that to a single read and single write.
Regard
Preet Kaur Walia
I think your code might support only the 4 burst case from the description below.
always @(posedge clk) begin if (w_complete_ns | reset) begin cnt <= {C_CNT_WIDTH{1'b1}}; end else if (whandshake_i) begin cnt <= cnt - 1'b1; end end always @(posedge clk) begin if (reset | w_complete_ns) begin subburst_last <= 1'b0; end else if ((cnt == {{C_CNT_WIDTH-1{1'b0}},1'b1}) & whandshake_i) begin subburst_last <= 1'b1; end end
Best regards,Yasuhiko Koumoto.