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can we delay read and write transactions(axi4) by providing delay in register slice?

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Basically I want to provide delay of 15 clock cycles  for writing and reading through axi4 bus .Is it possible?

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    Thank you so much for your replies.

    I am using memory controller block(Xilinx) and I need to delay the read and writes for 15 clock cycles so that I can modify the data being written to memory. Xilinx uses AXI bus . So I was thinking to delay the data when present in AXI bus. I have tried to delay the reading and writing but it has corrupted the data. I need to know where can I delay the data in AXI bus. And I have not made register slice myself . I was using the inbuilt AXI register slice to do so.

    All suggestions are welcome

    Regards

    Preet

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  • 0

    Thank you so much for your replies.

    I am using memory controller block(Xilinx) and I need to delay the read and writes for 15 clock cycles so that I can modify the data being written to memory. Xilinx uses AXI bus . So I was thinking to delay the data when present in AXI bus. I have tried to delay the reading and writing but it has corrupted the data. I need to know where can I delay the data in AXI bus. And I have not made register slice myself . I was using the inbuilt AXI register slice to do so.

    All suggestions are welcome

    Regards

    Preet

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