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can we delay read and write transactions(axi4) by providing delay in register slice?

Basically I want to provide delay of 15 clock cycles  for writing and reading through axi4 bus .Is it possible?

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  • Hi preet729,

    As "yasuhikokoumoto" says, we would need to know what is driving this requirement before anyone could suggest how to achieve this.

    The interconnect logic between your master and your slave should be trying to pass information as quickly as possible, so it would be rare to see anything intentionally adding 15 cycles of delay.

    Instead my first thought would be that if a master or a slave needs to delay any transfer completing on any channel, both the transfer source and the transfer destination have full control over the transfer timings using the AXI VALID and READY handshake signals.

    So if for example your slave required at least 15 cycles between an AW channel transfer and the first W channel transfer, the slave can simply hold WREADY low for that amount of cycles.

    Register Slices are there to break timing long paths, so adding up to a couple of clock cycles of latency depending on the design, but not 15.

    You can add buffers in some ARM interconnects to data channels, but these will still try to pass the data from source to destination as soon as possible, so just adding one cycle of registering before making the data available to the destination device. Write data channel buffers can have something called "tidemark" levels which will stall the buffered write data until sufficient write data is buffered, or until the WLAST data transfer, but again not really guaranteeing any 15 cycle requirement.

    So I would suggest that the component needing the 15 cycle delay should use the available READY and VALID handshake signals to implement the delay, unless you can explain why that isn't possible in your system, and what is driving this requirement.

    JD

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  • Hi preet729,

    As "yasuhikokoumoto" says, we would need to know what is driving this requirement before anyone could suggest how to achieve this.

    The interconnect logic between your master and your slave should be trying to pass information as quickly as possible, so it would be rare to see anything intentionally adding 15 cycles of delay.

    Instead my first thought would be that if a master or a slave needs to delay any transfer completing on any channel, both the transfer source and the transfer destination have full control over the transfer timings using the AXI VALID and READY handshake signals.

    So if for example your slave required at least 15 cycles between an AW channel transfer and the first W channel transfer, the slave can simply hold WREADY low for that amount of cycles.

    Register Slices are there to break timing long paths, so adding up to a couple of clock cycles of latency depending on the design, but not 15.

    You can add buffers in some ARM interconnects to data channels, but these will still try to pass the data from source to destination as soon as possible, so just adding one cycle of registering before making the data available to the destination device. Write data channel buffers can have something called "tidemark" levels which will stall the buffered write data until sufficient write data is buffered, or until the WLAST data transfer, but again not really guaranteeing any 15 cycle requirement.

    So I would suggest that the component needing the 15 cycle delay should use the available READY and VALID handshake signals to implement the delay, unless you can explain why that isn't possible in your system, and what is driving this requirement.

    JD

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