Barriers in in-order cores like cortex-A53, A7

Hi experts!

As you know, power efficient arm like cortexA7, A53 has in-order pipleline.
However as far as I understanding, Barriers like dmb, dsb, isb are related with out-of-order memory access.
But barriers are even used in in-order cpus.
What is for?
Can you explain when is useful or must be used barriers when in order cores?
Thank you