Hi experts!
As you know, power efficient arm like cortexA7, A53 has in-order pipleline.However as far as I understanding, Barriers like dmb, dsb, isb are related with out-of-order memory access.But barriers are even used in in-order cpus.What is for?Can you explain when is useful or must be used barriers when in order cores?Thank you
Hi oootha,
I am afraid that you might be misunderstanding with memory orders.
Even if several memory requests would be issued in-order, the response order would not be always in-order (i.e. sometimes out-of-order). The interconnects which were equipped in Cortex-A53 or A7 will be, so called, the multi-layer scheme and the response order will be defined according to the target device convenience.
Best regards,
Yasuhiko Koumoto.
Hi yasuhikokoumoto ,
Thank you for your answer!
It will be helpful.
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