why some instructions are not required to be  explicitly synchronized ?

Dear all:

In "ARM® Architecture Reference Manual ARMv8", B2.6.5 Concurrent modification and execution of instructions ,

it says some instructions, such as " B, BL, NOP, BRK, SVC, HVC, and SMC " dont need to be explicitly synchronized to instruction cache, while all other instruction need.

I can understand the latter, but no the case of "B, BL, NOP, BRK, SVC, HVC, and SMC ", can some body explain why?

Shen