Hi, expert. I'm making CacheFlush function by Virtual Address.
I'm using TTBR0 for user area, and TTBR1 for Kernel Area, and I'm using Dual core, Cortex-A9
I'm using Cache Flush Policy as Write Through about Kernel PageTable (Below KPT) itself, and Write Back-Write Allocate about Virtual Address.
When Core0 maps new virtual address (Below VA) in KPT
and Core1 access that VA which is already mapped by Core0,
Sometimes, Core1 makes Data Abort - Page Fault (accssing which refered above).
I try to find out the reason.. but I can't get any idea about this problem...
I'm begging your merciful and wise answer...
Hello,
I think you are misunderstanding.
Each core has TTBR0 and TTBR1, and an address translation is performed by each MMU. Therefore you should make the same mapping for the core1 as the core0 mapping.
By the way, the write through policy is identical to the uncached at Cortex-A9.
Best regards,
Yasuhiko Koumoto.
I already done as you say.
Each core has same TTBR1 value. (Cuz it is Kernel Area)
But TTBR0 can be different (It's user Area).
The problem is that though I used same TTBR1(regardless core) and one core maps VA to TTBR1 but another core can't see that area.
did you set TTBCR.PD0 (or bit 4) to '1' before TTBR1 address translation?
I try to use TTBR0 and TTBR1 both.. so if some VA is specified range, I use TTBR1 or TTBR0.
In case of me, I'm using TTBR1 for KERNEL and TTBR0 for USER.
So Both TTBR1 and TTBR0 are already enabled.
My understanding from ARMARM is that TTBR0 and TTBR1 would be exclusive. Therefore I think it would be impossible that both TTBR0 and TTBR1 are enabled at the same time. The switch of TTBR0 and TTBR1 would be TTBCR.PD0. Isn't my understanding correct?
Also please teach me how you enabled both TTBR0 and TTBR1?
Sorry to my late answer yasuhikokoumoto.
I think it's better to see ARM Architecture manual ArmV7-A nad ArmV7-R.
In this doc, section B4.1.143. It explains about TTBCR register, and PD0 and PD1 flags can be set each one not exclusive.
and Section B.3.5.4 explains How to use TTBR0 and TTBR1 both well.
Please refer these section. Thank you very much.
thank you for your input and correctiong me.
I had been misunderstood.
Let's go to the beginning.
Please let us know your setting of TTBR0, TTBR1 and TTBCR of each core.
Also let us know the VA which had occurred the problem.
At first, Sorry to my late answer to Yasuhiko Koumoto and Matt.
the problem happens on Kernel Address area.
But I think the hex address is not useful information to you
Thx,
Yun,
Levi
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