Hi,
I use Cortex-A17.
Any question.
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Example.1
memory-type is device.
1. LDR R0, [R2]
2. STR R3, [R4] (R2 != R4)
On AXI-bus, (2.)write transaction is wait for (1.)read response?
Example.2
memory-type is normal(noncache)
2. DMB
3. STR R3, [R4] (R2 != R4)
On AXI-bus, (3.)write transaction is wait for (1.)read response?
Example.3
memory-type is device or normal(nocache).
1. STR R0, [R2]
(DMB) for normal memory
On AXI-bus, (2.)write transaction is wait for (1.)write response?
Sorry...
Other words question.
What mean "ordered memory-access"?
- Is memory-request ordered ? (not wait for response)
or
- Is memory-complete ordered? (wait for response)
Please help me.
Thank you.
additional.
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On device type memory,
1.LDR R0,[R2]
2.LDR R1,[R3]
1.STR R0, [R2]
2. STR R1,[R3]
On AXI bus, Does (2.) wait for (1.)-response(RRESP or BRESP)?
(1.) and (2.) is same ID. but not wait for response?
On normal noncache type memory,
DMB
Is it so, too?
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