Hi everybody!!
I have a question on how get cache size on ARM v7-A, more specifically on A9 (or A7 or A15).
In accordance with the TRM at page 1529 I get the value from CSSIDR register and I compute the cache size. More precisely, I do cache size = num sets * num ways * line size.
So, the questions are two:
1) is the computation correct?
2) why the trm (at page 1529) reports: "The parameters NumSets, Associativity and LineSize in these registers define the architecturally visible parameters that are required for the cache maintenance by Set/Way instructions. They are not guaranteed to represent the actual microarchitectural features of a design. You cannot make any inference about the actual sizes of caches based on these parameters. "
Thanks a lot for the support!
John
Hi,
I think you should not read that statement independently.
It needs to be preceeded by that specific statement you had initially posted.
It just means you can't infer anything about internal design.
Regards,
Sudeep
Ok Sudeep,
You have reassured me!
Thanks!
BR
J.
Hi Sudeep,
thanks for the replay.
Do you mean that, for instance, banked caches are not visible from those values, right?
However, the strangeness for me is the sentence "You cannot make any inference about the actual sizes of caches based on these parameters."
Why?
BR,
Hi John,
1. Yes the computation is correct.
2. It means the values indicate what's visible to the user and you can't infer anything about microarchitectural design from those values.
E.g. A7 and A15 might have same values doesn't mean that they have exactly same design underneath in the hardware.
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