ARMv8 EL1 MMU

Hi,

    I am working on bootloader porting to ARM v8 platform. I am facing a problem in enabling MMU in execution level-1 EL1.

I am not able to set sctlr_el1.M bit when ever i try to set this bit the instruction won't complete. I think it is raising an exception where as i have not enabled the interrupts to capture. apart form sctlr_el1.M

bit i am able to set all other bits like sctlr.C, sctlr_el1.I.  Can some one please help regarding this issue? thanks in advance.

Parents
  • Hello,

    I think it is raising an exception where as i have not enabled the interrupts to capture.

    Keep in mind that you cannot mask synchronous exceptions, such as those caused by the MMU. The "DAIF" in DAIFSet and DAIFClr special registers only allow you to mask/unmask Debug, SError, IRQ, and FIQ exceptions.

    I am not able to set sctlr_el1.M bit when ever i try to set this bit the instruction won't complete.

    The most likely issue is that you have either misconfigured your translation regime (through the TCR_EL1 register), or you have misconfigured your translation tables, or a combination of both. You might be getting an Instruction Abort because the core fails to translate the virtual address of the next instruction, which would take you to your vector table, except the translation for that instruction may also fail, which would result in the core entering a recursive exception.

    The simplest way to narrow down what is going wrong is to check the value of the ESR_EL1 register (Exception Syndrome Register EL1) in a debugger immediately after single-stepping the write to SCTLR_EL1.M.

    Please can you try this and provide the value of ESR_EL1?

    Ash.

Reply
  • Hello,

    I think it is raising an exception where as i have not enabled the interrupts to capture.

    Keep in mind that you cannot mask synchronous exceptions, such as those caused by the MMU. The "DAIF" in DAIFSet and DAIFClr special registers only allow you to mask/unmask Debug, SError, IRQ, and FIQ exceptions.

    I am not able to set sctlr_el1.M bit when ever i try to set this bit the instruction won't complete.

    The most likely issue is that you have either misconfigured your translation regime (through the TCR_EL1 register), or you have misconfigured your translation tables, or a combination of both. You might be getting an Instruction Abort because the core fails to translate the virtual address of the next instruction, which would take you to your vector table, except the translation for that instruction may also fail, which would result in the core entering a recursive exception.

    The simplest way to narrow down what is going wrong is to check the value of the ESR_EL1 register (Exception Syndrome Register EL1) in a debugger immediately after single-stepping the write to SCTLR_EL1.M.

    Please can you try this and provide the value of ESR_EL1?

    Ash.

Children
More questions in this forum