Memory barrier (DSB, DMB). Does they guarantee writing data on cache to memory?

Hi Experts,

I'm reading white paper for ARMv7 and ARMv8.

but when i reading cache part and memory re-ordering, i have silly questions.....

Suppose there are below instructions..

 

Core A:

     STR R0, [Msg]

     STR R1, [Something]

Core B:

     DSB

     LDR R1 [Something] 

     ......

my questions are :

  • if Core A stores R1's data in its cache memory.. then does DSB guarantees R1's data also to be written on memory?
  • if first question's answer is not, Should i flush the cache for writing data on memory? like DCCSW

Cuz i really really beginner, maybe that situation is wrong itself....

But, i hope your merciful answer..

Thx.

Parents
  • Levi,

    it depends if the snoop-logic (SCU) is active for both cores. It keeps the caches in sync.

    The memory barrier is relevant for pipeline effects on _one_ core.

    E.g. you write to address A and then read from address B. If you do not want the reading to happen before the writing you need to add the memory barrier between.

    If SCU is not active between the cores you even have to flush A after writing and invalidate B before reading.

Reply
  • Levi,

    it depends if the snoop-logic (SCU) is active for both cores. It keeps the caches in sync.

    The memory barrier is relevant for pipeline effects on _one_ core.

    E.g. you write to address A and then read from address B. If you do not want the reading to happen before the writing you need to add the memory barrier between.

    If SCU is not active between the cores you even have to flush A after writing and invalidate B before reading.

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