Hi Experts,
I'm developing some kind of Secure OS on A57/53 big.LITTLE SoC.
While multi-core testing, I'm facing some wired problem on my world shared memory mechanism.
When I run world shared memory test on a single core (using affinity), it works well for a hundred of thousand times.
But once multi-core enabled, it sometimes fails.
Meaning to say, in the secure there is no content on the memory which is shared by non-secure.
I'm now doubting everything.
I believe that the CCI-400 works well between the big and LITTLE cluster's for cache coherency in the non-secure world.
But when world change occurs from non-secure to secure, does CCI-400 still guarantee cache coherency between two worlds?
Or Should I use any cache maintenance instruction?
My world shared memory mechanism is like this;
It might be a silly question, please advice me.
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