Reordering between multiple loads

Hello,

I have a question if following sequence of instructions involving post-indexed LDRs could be re-ordered on say Cortex A8:

To simplify, lets consider, r0 = 0xC, Cache line size 16 Bytes

ldr     r1, [r0], #4     /* 1 */

ldr     r2, [r0], #4     /* 2 */

ldr     r3, [r0], #4     /* 3 */

ldr     r4, [r0], #4     /* 4 */

/* At this point, r0 = 0x1C */

Now, will the above instructions always be executed in order 1-2-3-4 (because r0 is getting updated across) or there are chances that it could execute as 2-3-4-1 etc?

Thanks.

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  • It's going to depend on how the target address region is defined.

    If it is defined as Device (or Strongly Ordered), then the accesses would be observed in order.

    If it is defined as Normal, then the accesses could be observed out of order (that is, you could see 1-2-3-4 or 4-3-2-1 or 4-1-3-2, etc....).  It's also possible that the accesses might be merged together into a smaller number of accesses.  At a memory system level, if this is cacheable memory, all you are likely to see is a single cache line fill.

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  • It's going to depend on how the target address region is defined.

    If it is defined as Device (or Strongly Ordered), then the accesses would be observed in order.

    If it is defined as Normal, then the accesses could be observed out of order (that is, you could see 1-2-3-4 or 4-3-2-1 or 4-1-3-2, etc....).  It's also possible that the accesses might be merged together into a smaller number of accesses.  At a memory system level, if this is cacheable memory, all you are likely to see is a single cache line fill.

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