What's the single cycle Load-Use in ALU mean?(In Cortex-A7)

Hello,

According to http://www.arm.com/files/downloads/Enabling_Embedded_Innovation_with_the_Cortex-A7_Processor.pdf, it is described "The address generation unit is shifted one stage back in the pipeline to enable a single cycle load-use penalty".

I think this means the load can be performed in single cycle by pipelining.

The load pipe includes 2 stages and they would be the address generation and the L1 cache access.

In the same presentation material of ARM TechCon 2011, it is described "Single cycle load-use penalty in DPU".

Therefore, the load execution pipeline acts as the following.

        Addr1  Cache1

                    Addr2   Cache2

                                 Addr3   Cache3

                                              Addr4    Cache4

Best regards,

Yasuhiko Koumoto.

Hello,

According to http://www.arm.com/files/downloads/Enabling_Embedded_Innovation_with_the_Cortex-A7_Processor.pdf, it is described "The address generation unit is shifted one stage back in the pipeline to enable a single cycle load-use penalty".

I think this means the load can be performed in single cycle by pipelining.

The load pipe includes 2 stages and they would be the address generation and the L1 cache access.

In the same presentation material of ARM TechCon 2011, it is described "Single cycle load-use penalty in DPU".

Therefore, the load execution pipeline acts as the following.

        Addr1  Cache1

                    Addr2   Cache2

                                 Addr3   Cache3

                                              Addr4    Cache4

Best regards,

Yasuhiko Koumoto.