Coprocessor instruction differencies?

Are there differences between coprocessor instructions and instruction2:s?

I mean:

MCRR vs. MCRR2

MRRC vs. MRRC2

MCR vs. MCR2

MRC vs. MRC2

LDC vs. LDC2

STC vs STC2

I didn't find any differences in the encoding except the condition code, and no differences in the description of the functionality.

If there are no differences, are there any explanations why they are "condition-code-doubled"?

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  • Hello,

    I think it would be a very good question.

    I would like to know the truth, too.

    However, I guess the reason as extending the number of co-processors.

    That is, if the co-processor number was 0, target co-processors for ldc and ldc2 could be different.

    For example, regarding ldc instruction, the co-processor numbers of 10 and 11 indicate SIMD instructions.

    However, regarding ldc2 instruction, the co-processor number of 10 and 11 can indicate other than SIMD instructions.

    The below is the dis-assembler result.

       0xed910a01    vldrs0, [r1, #4]
       0xed910b01    vldrd0, [r1, #4]
       0xfd910a01    ldc210, cr0, [r1, #4]
       0xfd910b01    ldc2

    11, cr0, [r1, #4]

    They probably are not the same.

    How do you think about my idea?

    It would not be correct because the co-processor numbers of 10 and 11 for ldc2 would be UNDEFINED according to ARM ARM.

    After all, the above explanations would be nonsense.

    Best regards,

    Yasuhiko Koumoto.

Reply
  • Hello,

    I think it would be a very good question.

    I would like to know the truth, too.

    However, I guess the reason as extending the number of co-processors.

    That is, if the co-processor number was 0, target co-processors for ldc and ldc2 could be different.

    For example, regarding ldc instruction, the co-processor numbers of 10 and 11 indicate SIMD instructions.

    However, regarding ldc2 instruction, the co-processor number of 10 and 11 can indicate other than SIMD instructions.

    The below is the dis-assembler result.

       0xed910a01    vldrs0, [r1, #4]
       0xed910b01    vldrd0, [r1, #4]
       0xfd910a01    ldc210, cr0, [r1, #4]
       0xfd910b01    ldc2

    11, cr0, [r1, #4]

    They probably are not the same.

    How do you think about my idea?

    It would not be correct because the co-processor numbers of 10 and 11 for ldc2 would be UNDEFINED according to ARM ARM.

    After all, the above explanations would be nonsense.

    Best regards,

    Yasuhiko Koumoto.

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