Cortex-A7 pipeline is non-symmetric, what does this attribute mean?
My understand is that cortex-A7 pipeline's five entries does not have the same two, in the contrary, the cortex-A15 have the two entries are the same.
I agree with you.
I guess "integer pipe" and "dual issue" pipe are almost the same but they are not equal.
Therefore, they are called as non-symmetric.
The second slot of the dual issue in the A7 could mainly only do integer instructions whereas for the newer A53 it can do most of the things the first slot can do. Symmetric in general means interchangeable and the issue slots of the A7 are nowhere near equivalent whereas those for the A53 are nearly so.
I see that your question got already answered.
Actually, it's very odd to see the term "symmetric"/"non-symmetric" used in reference to a processor pipeline; the term "symmetric/non-symmetric" is sometimes used in multi-core processors to describe "identical/non-identical" cores. In the context of the processor pipeline, "symmetric pipelines" means that the symmetric pipeline can execute the same type of instruction in the same manner with the exact same latency. For example, some processors might have identical integer pipelines that execute with different latencies to save energy. Therefore, "non-symmetric" can mean that: (a) different integer pipelines have different latencies (highly unlikely here as I am not aware of any other commercial processor that implements this technique) or (b) some integer pipelines can only execute certain types of instructions similar to the dual-issue Cortex-M7 where the second integer pipeline can only execute a subset of integer instructions. I am not familiar with the A7 but the third integer pipeline means that is capable of issuing up to 3 integer instructions per cycle which is quite impressive but again this diagram is very basic and should not be used as a technical reference.
BTW, where did you find the "non-symmetric pipeline" reference. A search for the term on infocenter.arm.com reference 0 hits?
Thanks very much for your answer.
Your answer give me so much help.
And for your question, I find the "non-symmetric pipeline" in the arm's white paper about the big.LITTLE.
You're very welcome and thanks for the link. There is hardly any details on the A7 architecture in that document.
Here is on old post that asks a similar question Cortex-a7 dual-issue? Surprisingly you can find out more details on the A7 arch from the GNU machine description file than ARM docs (I went through the whole A7 TRM and couldn't find a single reference to dual-issue apart from the disable bit in ACTLR)! The cortex-A7.md file has some insightfully comments that makes it a lot easier to decipher if you're not familiar with the syntax.
Yep that and the LLVM is where one often sees things first
I just had a look and they seem to have just made a mess of the gcc trunk as the arm and aarch64 directories have disappeared from trunk/gcc/config. Now I very much hope that is not a glimpse into the future!
I think it is unbeliveable!!!
I go to the site, there is no arm or aarch64 directories!
Sorry that was just the first page of results. Silly me. I normally sort by date and arm then normally occurs near the beginning.
We are all too careless!
Hi,Just found this subject :)This specificity seems interesting to me. Finally, only in the context of a hypervisor, does this allow two data streams to be passed on a single interrupt call ?Regards,Jerome
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