Hi all,
Im working on Keystone II Tci6638k2k(4arm+8dsp) custom design board with u-boot. I understand that how u-boot working.
U-boot gives entry point to other cores. Other cores take program counters with this way. But i want to give core registers too. Is it possible? Can primary arm access secondary arm's registers?
Best Regards.
Srt
Hello
No, in the Tci6638k2k a Cortex-A15 core cannot access the general purpose registers (r0 -r15) or CP15 registers of another Cortex-A15 core. the communication will have to happen via an external memory-mapped location (or alternatively, using software-generated interrupts).
-Duberly
Seem this is not possible. I wanted something similar, but have never received a positive answer to this question Can one ARM core debug another one in an MP/bigLITTE system?
Hello,
you can independently set the register values for each core by using CPU ID register.
For example, the following code will can be used.
MRC p15,0,r0,c0,c0,5 @ returns CPU ID register and r0,r0,#0x3 cmp r0,#0 beq core0_set cmp r0,#1 beq core1_set cmp r0,#2 beq cpre2_set cmp r0,,#2 beq core3_set .......... core0_set: <set core0 registers> core1_set: <set core1 registers> core2_set: <set core2 registers> core3_set: <set core3 registers>
Isn't this your intention?
Best regards,
Yasuhiko Koumoto.
Wouldn't this be possible, if making connections to the device's own debug interface using GPIO pins ?
I know it might not be the most interesting way to do it, but if an external debugger can do it, I believe it should be possible to make a workaround-hack.
Hi,
in the code you are providing you are able to have different core register setting depending on the core ID. But initial question was a way to set core 1 register from core 2. And that is not possible using any kind of instruction. The only way is to have :
- core 1 setting Core 2 register value in memory
- core 2 is having dedicated software in charge of reading this memory to get value and set its own register.
Br
Sebastien
Hello Sebastien,
thank you for correcting me. I had misunderstood.
I think your method would be the most appropriate.
Hi Sebastien,
You are correct. The only way for setting secondary core's registers is make them to changed itself. So this works;
- Primary arm can give only entry point adress to secondary arms (i give them fake entry adresses)
- Secondary arms entry point points a function (this function used for setting own core registers)
- At the end of function secondary arms jump to real entry adress.
So primary arm gives only a function pointer adress for entry point to secondary arms.
Secondary arms run this function first, and jump real code start adress.
Thank you for your responses.
Interesting Idea, I might try this in the RasPi2 actually. But I wonder if we can convince somebody to implement this in real world devices.
Hi Axel,
If Core 0 has access to Core 1's memory-mapped debug registers then it is possible to halt that core, and use the DBGITR and DBGDRRTX etc. to push instructions and data through it to do this. It is a little more complex than that, but it's possible. External debug might be enacted over JTAG via something like a DSTREAM but it is exactly the same model to have another core be the debug agent. This is thanks to CoreSight being just another set of memory-mapped peripherals, and every debug transaction boiling down to a write to memory on one bus or another.
Whether each core can see the other's debug registers is totally down to the system designers, though - there's no requirement to hook up the debug APB to system space, so it may only be possible to get to this interface via the DAP.
As for seeing it in real world devices, they do exist.. unfortunately even if I could think of one right now, I don't think I could advertise it.
Ta,
Matt Sealey, Senior Applications Engineer, PEG
Yes and no. If you start a TrustZone monitor on the second core (if possible on Keystone), then you can start the application on the second core with any register values you want.
What methods are used to write the PC for secondary cores? I can't find that documented anywhere. The reference manual is quite large.
Branden Sherrell said:The reference manual
What is "The reference manual"? There are plenty outside.