When two clusters(Big/Little) exist in SoC, the timer can be used to support Synchronization between two clusters.
But How to understand "Synchronization", anybody can tell me some typical application context? I am really confused......
And, if only one cluster exists in SoC, the timer is unnecessary? if not, Why use it......
Within each core you have a number of comparators. You set the the comparator to a value, and it will then generate an interrupt when the Count reaches (or exceeds) the value of the comparator. The Count is generated by a system level component, usually referred to as the System Counter. This exports the _same_ count to _all_ the cores. Giving all the cores a common view of time.
The sort of thing you use this for is OS schedulers. In a SMP OS you want to run the scheduler at regular intervals on all cores. But, you don't want more than one core to try to run the scheduler at the exactly the same time, as that would lead to contention. The solution is to set staggered values in the comparators, meaning the scheduler interrupt goes off at staggered times on each core.
Thanks, Martin.
I take your point about system timer provides the same count value for all the cores whatever the cores located in one cluster or two different clusters.
Typically, the system timer used for OS schedulers. Your reply is very useful for me.
But, now I have another question, this kind of generic timer is not present in ARMv7.
Such as the Cortex-A9, the processor does not have the system timer interface signals, meaning the OS that runs on CA9 processors does not use system timer to schedule the cores? or the OS selects other ways to complete scheduling, and what other ways?
But, now I have another question, this kind of generic timer is not present in ARMv7. Such as the Cortex-A9, the processor does not have the system timer interface signals, meaning the OS that runs on CA9 processors does not use system timer to schedule the cores? or the OS selects other ways to complete scheduling, and what other ways?
The Generic Timer is an optional extension in ARMv7-A. It's present on the Cortex-A15 and Cortex-A7, but not on the Cortex--A9 and Cortex-A5.
The Cortex-A9/Cortex-A5 have something similar, which is the Global Timer. Where all the cores in a given processor share a global count:
Cortex-A9 MPCore Technical Reference Manual: 4.3. About the Global Timer
The Cortex-A9/A5 also do not support multi-processor coherency (i.e. they don't support a cache coherent bus protocol). So the limitation that the count is only "global" to the cores of one processor is unlikely to be a problem.
Thank you very much for your nice answer. Martin.
Now I know that the "generic timer" in Cortex-A53 is just similar with the "global timer" of Cortex-A9. This is very useful for me to understand the design purpose of these timers
And, because the CA9 processor do not support the cache coherency among clusters, the extension of generic timer may not be necessary. The global timer is enough for the Synchronization among cores of one cluster.
Thanks again
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