If a region is marked as non-cacheable, will the CPU also first check the cache when CPU want to access the region?
In cortex-A7 spec, it says" the core hardware will check all instruction fetches and data reads or writes in the cache, although obviously you must mark some parts as non-cacheable". So I want ask the above question.
Architecturally it's not required to, so relying on this behaviour is not wise, but it will generate cache checks on some cores.
HTH,
Pete
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