Please explain non-temporal example in programmer's guide

In

ARM Cortex-A Series Programmer’s Guide for ARMv8-A: 13.2.4. Non-temporal load and store pair

it talks about a relaxation of the memory ordering requirements and then gives the example


     LDR     X0, [X3]

     DMB     NSHLD

     LDNP   X2, X1, [X0]

saying the memory barrier is needed otherwise it might read from an unpredictable address. I don't follow this at all,it just seems wrong to me.

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  • What's wrong about it?

    It's a relaxation in the memory model which allows faster performance for some use cases (uncached streaming reads from an external media device, for example) if the microarchitecture wants to exploit it, and as such as some "odd" behaviour. This is simply saying that if you want predictable behaviour interoperating with other loads and stores, you need a barrier. In general this isn't the kind of instruction which a C compiler would normally be emitting (at a guess) - it's a niche use case not general purpose programming.

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  • What's wrong about it?

    It's a relaxation in the memory model which allows faster performance for some use cases (uncached streaming reads from an external media device, for example) if the microarchitecture wants to exploit it, and as such as some "odd" behaviour. This is simply saying that if you want predictable behaviour interoperating with other loads and stores, you need a barrier. In general this isn't the kind of instruction which a C compiler would normally be emitting (at a guess) - it's a niche use case not general purpose programming.

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