How SMMU will override the memory attribute of the master which have MMU/MPU embedded?

For example, one M4 is a client of SMMU, and its MPU had been configured to map some memory(MEM_A) as inner outter write-back, how the configureation of SMMU context transcation table will affect the access attribute, say, the transcation table mark   MEM_A as non-cachebale/non-bufferrable? Or if its SMMU_CBn_SCTLR's M bit is 0?