I am reading SMMU spec V2.0, and wondering why no C bit in SMMU_CBn_SCTLR. There is M bit in it.
Thanks a lot, Martin.
The SCTLR.C bit in the ARM architecture enables the data and unified caches. The SMMU does not include data/unified caches. Any caching would be done by a separate cache block, which would have it's own enables.
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