General Feature of Cortex processors on cache coherency

Hi Experts,

Is there any general feature available in the cortex processors to realize the cache lines by DMA through AXI ?

I found some features like CCI module available to provide this feature in multi-core environment. Other than that, is it possible to connect the DMA engine alone with processor in realization of the same or it is a special feature provided by ARM ?

Regards,

Techguyz