hi ,
I want to know the cycle information ,latencies of each instruction(secially vector instructions in A32 and A64) in coretex A53 architecture. It seems there is no document available which specifies the cycle timings. Can any one please provide the information.Fast response will be appreciated.
Thanks,
Sujatha.
Just read Chris' answer, the "theory" might not match the real life, as the cycle counts in a core manual do not reflect bus interactions.If you do not trust the performance counters, use another "time base", for example a timer in the SoC.