I want to know the cycle information ,latencies of each instruction(secially vector instructions in A32 and A64) in coretex A53 architecture. It seems there is no document available which specifies the cycle timings. Can any one please provide the information.Fast response will be appreciated.
Can any one provide the information about cortex A -53 cycle information for instruction set.Fast response will be helpful for us.
Thank you for your question.
I'm afraid we do not publish this kind of detail for most of our processor cores, especially for the newer ones. May I ask what you are trying to achieve? Perhaps I can help in some other way?
Thank you for the reply.
I want to estimate how many cycles and latency's that a small portion of C code will take using AARCH64 and ARCH32 instruction set.I mean how many cycles generally it needs to execute the small portion of code?
Thanks for the extra information. In these situations, our suggestion is to use the performance counters in the processor to count cycles over short sequences. These are quite easy to use and well documented.
However, you should be aware that the cycle count information is not just dependent on the processor. Often the memory effects are much, much larger. If your sequence contains memory accesses, then the latency of these. and the resulting pipeline effects, are usually much greater than the cycles taken by the processor's execution units. They are also unpredictable, due to the non-determinate nature of cache behaviour.
The performance counters will show you the total effect of processor and memory, as well as allowing you to separate out stalls and latencies. A simple analysis of execution cycles taken from a manual will not show you any of this and is often not much use at all.
Hope this helps.
Do you have any news about the availability of this guide for ARMv7-A ( Cortex A53) , with the number of cycles for each instruction?
I have to compare this theoretical number with the one I found reading the "Cycle Counter Register", so I can validate the value I am reading. Fast response will be appreciated.
Thank you in advance,
Just read Chris' answer, the "theory" might not match the real life, as the cycle counts in a core manual do not reflect bus interactions.If you do not trust the performance counters, use another "time base", for example a timer in the SoC.
View all questions in Cortex-A / A-Profile forum