hi ,
I want to know the cycle information ,latencies of each instruction(secially vector instructions in A32 and A64) in coretex A53 architecture. It seems there is no document available which specifies the cycle timings. Can any one please provide the information.Fast response will be appreciated.
Thanks,
Sujatha.
Thanks for the extra information. In these situations, our suggestion is to use the performance counters in the processor to count cycles over short sequences. These are quite easy to use and well documented.
However, you should be aware that the cycle count information is not just dependent on the processor. Often the memory effects are much, much larger. If your sequence contains memory accesses, then the latency of these. and the resulting pipeline effects, are usually much greater than the cycles taken by the processor's execution units. They are also unpredictable, due to the non-determinate nature of cache behaviour.
The performance counters will show you the total effect of processor and memory, as well as allowing you to separate out stalls and latencies. A simple analysis of execution cycles taken from a manual will not show you any of this and is often not much use at all.
Hope this helps.
Chris