Hi all.
I have general questions on why certain features of the AXI4 protocol are the way they are.
AXI4 allows a master to send the data beats before sending the address information.
I'm curious to know if this is advantageous, either in systems with a single pair of Master-Slave, or in larger systems with AXI interconnect.
It is not that the write data and write address are completely independent - The master has to know the address before sending the data - because the correct byte lanes on the data bus and the wstrb signal has to match the address alignment.
So if the master already knows the address, why not send it?
Thanks.
Hi af_23,
I suppose that in the case of address translation, the write data is actually available in the master before the translated address. Maybe this could be one reason?
Hi, thank you for your reply.
Can you please elaborate on address translation? What does this process mean?
Address translation commonly happens in a CPU, where a virtual address goes through the MMU and is translated to a physical address. That was just an example where computations happen on the write address and not on the write data.
Thanks for the explanation.
But in this case, wouldn't the write data + strobe need to match the physical address (the actual address being sent)?
Therefore, the data beat still isn't ready until the translation process completes, so I don't think this is a valid case for sending the data before the address.