I have general questions on why certain features of the AXI4 protocol are the way they are.
AXI4 allows a master to send the data beats before sending the address information.
I'm curious to know if this is advantageous, either in systems with a single pair of Master-Slave, or in larger systems with AXI interconnect.
It is not that the write data and write address are completely independent - The master has to know the address before sending the data - because the correct byte lanes on the data bus and the wstrb signal has to match the address alignment.
So if the master already knows the address, why not send it?
I suppose that in the case of address translation, the write data is actually available in the master before the translated address. Maybe this could be one reason?
Hi, thank you for your reply.
Can you please elaborate on address translation? What does this process mean?
Address translation commonly happens in a CPU, where a virtual address goes through the MMU and is translated to a physical address. That was just an example where computations happen on the write address and not on the write data.
Thanks for the explanation.
But in this case, wouldn't the write data + strobe need to match the physical address (the actual address being sent)?
Therefore, the data beat still isn't ready until the translation process completes, so I don't think this is a valid case for sending the data before the address.
As well as the valid scenario described by vstehle (where to answer your latest question the address translation is very unlikely to change the address LSBs, and so affect the data positioning and strobes), another scenario where W leads AW is when you add more registering on the AW path compared to the W path between the source and destination of the transaction. This registering would be added to ease timing on long paths, and isn't always the same requirement for all channels.
As to why allowing W before AW is advantageous, in most master designs I can think of the W data will come out at the same time as the AW, or after it (although it is feasible you might know the data to send before you have worked out the address).
In any interconnect logic the address decoders will need to know the address before they can route the data, so any early W transfer could be stalled by holding WREADY low until the interconnect has decoded the AW transfer. But after the address decode, as I described it is possible to see timing isolation registering on the AW channel such that the W transfer could come out of the interconnect ahead of data.
So the protocol doesn't have any reason to restrict W before AW, and if any component needs a specific ordering it can stall any transfer using the xVALID/xREADY handshakes.
Thank you for your great reply. It's much clearer now.