I am concerned about a situation where code running on one processor core is writing to L2 cache register(s) to flush (Clean and Invalidate Line by Physical Address operation) one address from the L2 cache while code running on a different processor core is also writing to the same L2 cache registers to flush a different address from the L2 cache.
The L2C-310 documentation says that the Clean and Invalidate Line by PA operation is an atomic operation, and that it stalls the slave ports until it is completed. I am not sure how to interpret that - does it mean that if two successive writes (from code on two different processor cores) are made to the reg7_clean_inv_way register, that the 2nd write operation would wait until the completion of the Clean and Invalidate Line by PA operation initiated by the first write?
Or could there be a case where "Any write to a writeable register returns SLVERR while a background operation is in progress"?