ARM Cortex A8 : Enabling D Cache aborts

I am using Omap3515 (Arm Cortex A8). Enabled I-Cache, D-Cache, Branch Prediction and MMU.

I am getting a data abort, if I try to copy a frame buffer of 600KB from an external memory region to another external memory region. After the data abort, I could notice that the SDR i.e SDRAM is not accessible.

I have enabled MMU in such a way that PA=VA.

There is no issue if I copy less amount data.

And also, If I disable D-Cache then there is no abort and it works fine. But I would like to enable D-Cache for faster access.

Thanks and regards,

Gopu

Parents
  • Hello Gopu,

    how did you solve the problem which the internal RAM access was slower than the external RAM when MMU was enabled?

    In case of successful case, how many data did you transferred?

    Is it less that dcache size?

    By the way, what is your computer board of OMAP 3515?

    What is the LPDDR part?

    Best regards,

    Yasuhiko Koumoto.

Reply
  • Hello Gopu,

    how did you solve the problem which the internal RAM access was slower than the external RAM when MMU was enabled?

    In case of successful case, how many data did you transferred?

    Is it less that dcache size?

    By the way, what is your computer board of OMAP 3515?

    What is the LPDDR part?

    Best regards,

    Yasuhiko Koumoto.

Children
More questions in this forum