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interrupt signal when performing world switch on GICV3/4

林军

We have a question on the interrupt signal when performing world switch.

  1. Suppose the CPU is running in secure world (TEE). An interrupt(Non secure Group1) is generated from REE.
  2. With SCR_EL3.FIQ==0, it will be signaled as an FIQ, the exception is taken to S-EL1.
  3. EL3 performs world switch.
  4. Now the PE is in Non-secure stat, the interrupt is IRQ.

Does the GIC/CPU interface generate an extra interrupt signal when detecting world switch(NS-bit flop) with GICv3? Or is it still the same interrupt signal but only recognized as IRQ when switched to non-secure world?

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    I believe that you are saying,

    With SCR_EL3.FIQ==1, it will be signaled as an FIQ, the exception is taken to S-EL3.

    >Or is it still the same interrupt signal but only recognized as IRQ when switched to non-secure world?

    No, it is still FIQ/IRQ connecting to CPUs.

    Since GICv3 GIC CPU interface is coupled with CPU in processor, so the CPU interface hardware would know CPU's EL and secure state information, GIC CPU interface can signal IRQ or FIQ basing on CPU EL and secure state for group 1 interrupts.

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  • 0

    I believe that you are saying,

    With SCR_EL3.FIQ==1, it will be signaled as an FIQ, the exception is taken to S-EL3.

    >Or is it still the same interrupt signal but only recognized as IRQ when switched to non-secure world?

    No, it is still FIQ/IRQ connecting to CPUs.

    Since GICv3 GIC CPU interface is coupled with CPU in processor, so the CPU interface hardware would know CPU's EL and secure state information, GIC CPU interface can signal IRQ or FIQ basing on CPU EL and secure state for group 1 interrupts.

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