interrupt signal when performing world switch on GICV3/4

We have a question on the interrupt signal when performing world switch.

  1. Suppose the CPU is running in secure world (TEE). An interrupt(Non secure Group1) is generated from REE.
  2. With SCR_EL3.FIQ==0, it will be signaled as an FIQ, the exception is taken to S-EL1.
  3. EL3 performs world switch.
  4. Now the PE is in Non-secure stat, the interrupt is IRQ.

Does the GIC/CPU interface generate an extra interrupt signal when detecting world switch(NS-bit flop) with GICv3? Or is it still the same interrupt signal but only recognized as IRQ when switched to non-secure world?

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