Please let me know that how to design AXI slave and do its verification? If we design AXI slave using system verilog(its hdl part) then for verification what do we need to write ?I mean master would be as VIP? and How do we verify please give a general idea in steps.
Does anyone have boom recommendations for designing or verifying AXI or AHB protocol ? Also can someone tell me why so many people implement their own version of it!!!
My first reply in this thread should apply for verifying any design, not necessarily specific to AXI.
For your second question, by "it" do you mean a verification environment, or their own version of the protocol ?
If the answer to "it" is verification environment, each device you want to test will have its own features you might need to test, so although you could have the same test environment to drive stimulus, the test vectors would be specific to the DUT to exercise all its supported functions.
But for the protocol question, I'd expect most people will stich to following the protocol, and implementing the features they want to support (so supporting all possible inputs, even if just to signal an error for any unsupported request). If they don't and do their own thing, it is likely they'll have issues connecting to other IP designed to that protocol.
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